CustomLogic is an FPGA design kit from Euresys enabling the design and upload of FPGA code to a Coaxlink board. It is compatible with the Coaxlink Octo and Coaxlink Quad CXP-12. Up to 70% of their Xilinx Kintex Ultrascale XCKU035 FPGA resources are available. The design phase uses the Xilinx Vivado development tools. CustomLogic is the ideal solution for full custom even proprietary code.
At a glance
• FPGA design kit enabling the design and upload of FPGA code to a Coaxlink board
• Supported by Xilinx Vivado development tool
• Compatible with Coaxlink Octo and Coaxlink Quad CXP-12: 70% of Xilinx Kintex Ultrascale XCKU035 FPGA resources available
• Access to CoaXPress camera pixel stream, on-board DDR4 memory and PCIe Gen3 connectivity
• Memento Event Logging messaging
The Data Stream interface is based on the AMBA AXI4-Stream protocol. On the source side, this interface provides the user logic with images acquired from a CoaXPress Device (for example a CoaXPress camera). On the destination side, the Data Stream interface transfers the resulting images/data generated by the user logic to the PCI Express DMA Back-End channel.
The DDR4 Memory interface is based on the AMBA AXI4 protocol.
The Memento Event interface allows the User Logic to send timestamped events to the Memento Logging tool with a precision of 1 μs. Along with the timestamped event, two 32-bit arguments are reported in Memento. The Control/Status interface allows the user to read and write registers inside the user logic via the Coaxlink Driver API.
The Coaxlink CustomLogic SDK is delivered with a reference design intended to be used as a template. The reference design exposes all interfaces available to the user. It is a Xilinx Vivado project with the following functional block diagram:
Using CustomLogic does not require any additional hardware. The 3613 JTAG Adapter Xilinx for Coaxlink (which can be purchased separately) allows connecting the Xilinx programmer to the Coaxlink FPGA for debugging purposes.