Smaller design nodes are now far more costly and much harder to achieve. So interest has turned to approaches that do more at the package level.
Chiplet Summit, taking place January 23 to 25 2025 at the Santa Clara Convention Center, California, helps educate both design and packaging engineers. The advanced packaging tutorial covers methods such as 3D, wafer-scale, and panel-scale. The Working with Foundries tutorial then shows how such approaches have become part of manufacturing. Later sessions deal with finding the right package for an application, as well as short-term and long-term trends.
The Summit also offers major company keynotes, expert tables, panels, and paper sessions. An exhibit hall has key products from industry leaders.
“Chiplet Summit helps designers profit from major advances in packaging,” said Chuck Sobey, Summit General Chair. “Designers and packagers can both learn how to develop SiPs (systems-in-package), use die-to-die interfaces such as UCIe, and create supercomputers in a package.”
Chiplet Summit, a product of Semper Technologies, covers the applications, key technologies, and leading vendors that drive the chiplet market.
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